Over the recent years, copper wiring has been adopted as a wiring material for CMOS LSI (Complementary Metal Oxide Semiconductor Large Scale Integration) in terms of reducing wiring resistance and enhancing durability of electro migration (EM) and stress migration (SIV: Stress Induced Voiding).
Copper (Cu) is hard to work the wiring by dry etching unlike aluminum (Al) that has hitherto been employed. Such being the case, formation of the copper wiring generally involves adopting a damascene method of forming a trench becoming the wiring and a via becoming a contact in an insulating film and forming the wiring by embedding the copper therein, and a dual damascene method of forming the trenches becoming the wiring and the via and integrally forming the wiring and a plug by embedding the copper therein. Generally the copper layer is electrodeposited onto a substrate in terms of mass productivity and costs.
The electrodeposited copper film based on the damascene method is mixed with impurities such as oxygen (O), carbon (C), sulfur (S), chlorine (Cl) and nitrogen (N), and it is known that the in-wiring impurities affect the durability of the EM, the SIV, etc (refer to, e.g., Non-Patent documents 1 and 2).
In a copper wiring forming process of a general type of Cu/Ta(N) wiring structure, the EM and the SIV are in a trade-off relationship. Namely, if a wiring width is narrow, a problem about the durability against the EM arises but is solved by decreasing a concentration of the impurity. Whereas if the wiring width is wide, a problem about the durability against the SIV arises but is solved by increasing the concentration of the impurity.
Accordingly, when forming the copper wiring, it is desirable to adjust the concentration of the impurity corresponding to the wiring width. Further, the impurity in the electrodeposited copper film is thermally diffused in an annealing process after the electrodeposition, and it is therefore necessary to adjust the concentration of the impurity, including a behavior of the diffusion.
Note that Patent document 1 discusses a technology of forming the copper wiring exhibiting the high durability against the EM by electrodeposited copper composition containing the impurity and diffusing the impurity within a copper seed layer after growing the copper seed layer.
Moreover, Patent document 2 discusses a technology of decreasing the impurity concentration of the grown copper electrodeposited film by taking a wafer out of a plating solution in a state of applying a voltage.
Further, Patent document 3 discusses a technology of forming the copper film exhibiting the high durability against the EM by staking the impurities.
The following are examples of related art of the present invention: Influence of Copper Purity on Microstructure and Electromigration, B. Alers, et al. (IEEE 2004), Design of ECP Additive for 65 nm-node Technology Cu BEOL Reliability, H. Shih, et al., (ITC 2005), Japanese Patent Laid-Open Publication No. 2004-158897, Japanese Patent Laid-Open Publication No. 2006-40908, Japanese Patent Laid-Open Publication No. 2000-174025, and Japanese Patent Laid-Open Publication No. 2006-32545.